128Mb: x16 Mobile SDRAM
Operation
last desired data element of a longer burst that is being truncated. The new READ
command should be issued x cycles before the clock edge at which the last desired data
element is valid, where x = CL - 1.
This is shown in Figure 10 on page 20 for CAS latencies of two and three; data element n
+ 3 is either the last of a burst of four or the last desired of a longer burst. The 128Mb
SDRAM uses a pipelined architecture and therefore does not require the 2 n rule associ-
ated with a prefetch architecture. A READ command can be initiated on any clock cycle
following a previous READ command. Full-speed random read accesses can be
performed to the same bank, as shown in Figure 11 on page 21, or each subsequent
READ may be performed to a different bank.
Data from any READ burst may be truncated with a subsequent WRITE command, and
data from a fixed-length READ burst may be immediately followed by data from a
WRITE command (subject to bus turnaround limitations). The WRITE burst may be
initiated on the clock edge immediately following the last (or last desired) data element
from the READ burst, provided that I/O contention can be avoided. In a given system
design, there may be a possibility that the device driving the input data will go Low-Z
before the SDRAM DQ go High-Z. In this case, at least a single-cycle delay should occur
between the last read data and the WRITE command.
Figure 9:
READ Command
CLK
CKE
CS#
RAS#
CAS#
WE#
A0–A8
HIGH
COLUMN
ADDRESS
A9, A11
ENABLE AUTO PRECHARGE
A10
DISABLE AUTO PRECHARGE
BA0, BA1
BANK
ADDRESS
DON’T CARE
PDF: 09005aef8237e877/Source: 09005aef8237e8d8
128Mb_x16 Mobile SDRAM_Y25M_2.fm - Rev. C 2/07 EN
19
Micron Technology, Inc., reserves the right to change products or specifications without notice.
?2006 Micron Technology, Inc. All rights reserved.
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